The present invention generally relates to digital filters, and more particularly to a finite-impulse response (FIR) filter that is reconfigurable for different sets of canonical sign digit (CSD) coefficients.
One technique for implementing FIR filters is the CSD representation. This technique provides a substantial advantage in the hardware implementation of FIR filters by eliminating the need for multipliers, which are the largest and most expensive components required to perform digital filtering operations. Instead, the CSD representation permits the minimization of the total number of non-zero bits in all of the filter coefficients that nevertheless maintains acceptable filter performance.
For each tap in a CSD representation filter, the data tap value is shifted by the number of bit positions corresponding to the position of each non-zero bit in the coefficient for that tap. The resulting shifted data tap values are then added. This is done for every coefficient in the filter. A primary consequence of this is that a larger adder (i.e., one with more data inputs) is required than would be needed for a conventional FIR filter implementation. However, this is still desirable since no multipliers are used. The high hardware cost of multipliers makes the CSD implementation especially attractive for very long digital filters. Such filters are often needed, for example, in communications systems, particularly for the demodulation of digital data signals.
In CSD filters, each coefficient is implemented by adding the associated data tap value shifted by a coefficient bit position. Since the shifting of the data tap values is usually a hard-wired function of the data bus, CSD filters are designed exclusively for a specific set of coefficients and thus cannot be reconfigured or programmed for different coefficients. This is in contrast with a conventional FIR filter, in which each coefficient is simply multiplied by the data tap value. Such a filter can easily be reconfigured if a programmable register is provided at the coefficient input of each data tap multiplier, so that every coefficient can be reconfigured to any desired value simply by programming that value into the register.
The present invention is directed to a reconfigurable or programmable FIR filter having coefficients that are represented using the canonical sign-digit (CSD) format. According to the present invention, the FIR filter can be reconfigured at any time by specifying (i.e., programming) different values for the coefficients, limited only by the constraints of maximum values for filter length, data and coefficient precision.
The FIR filter according to the present invention includes a shift group associated with at least one of the data tap values and at least one of the CSD coefficients. Each shift group includes a plurality of parallel paths. Each parallel path shifts the data tap value according to a bit pair of the coefficient to produce a weighted product. An adder is also included that combines the weighted products from each of the shift groups.
Further, each parallel path includes a shifting unit for shifting the data tap value a predetermined number of places corresponding to a position within the coefficient of a first bit of the bit pair. Each parallel path further includes an adder-input unit coupled to an output of the shift unit for further shifting the data tap value if a second bit of the bit pair is non-zero. The adder-input unit also passes the data tap value from the shifting unit unchanged to the adder if the second bit of the bit pair is zero. The adder-input unit also forces the data tap value from the shifting unit to zero if both bits of the bit pair are zero. The adder-input unit further inverts the data tap value from the shifting unit if one bit of the bit pair is negative.
The present invention is also directed to a method for processing a digital filter tap value with a canonical sign digit (CSD) coefficient. The method includes replicating the digital filter tap value to produce replicated tap values. The method also includes shifting each of the replicated tap values according to a bit pair of the CSD coefficient to produce weighted products and then adding the weighted products.